Optimizing Video Application Design for Phase-Change RAM-Based Main Memory
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Sunggu Lee | Sungjoo Yoo | Jinpyo Park | Suknam Kwon | S. Yoo | Sunggu Lee | S. Kwon | Jinpyo Park
[1] Wei Xu,et al. Data manipulation techniques to reduce phase change memory write energy , 2009, ISLPED.
[2] 裕幸 飯田,et al. International Technology Roadmap for Semiconductors 2003の要求清浄度について - シリコンウエハ表面と雰囲気環境に要求される清浄度, 分析方法の現状について - , 2004 .
[3] Engin Ipek,et al. Dynamically replicated memory: building reliable systems from nanoscale resistive memories , 2010, ASPLOS XV.
[4] Rami G. Melhem,et al. Increasing PCM main memory lifetime , 2010, 2010 Design, Automation & Test in Europe Conference & Exhibition (DATE 2010).
[5] Onur Mutlu,et al. Architecting phase change memory as a scalable dram alternative , 2009, ISCA '09.
[6] Hsien-Hsin S. Lee,et al. SAFER: Stuck-At-Fault Error Recovery for Memories , 2010, 2010 43rd Annual IEEE/ACM International Symposium on Microarchitecture.
[7] Jose Renau,et al. Effective Optimistic-Checker Tandem Core Design through Architectural Pruning , 2007, 40th Annual IEEE/ACM International Symposium on Microarchitecture (MICRO 2007).
[8] Karin Strauss,et al. Use ECP, not ECC, for hard failures in resistive memories , 2010, ISCA.
[9] Hsien-Hsin S. Lee,et al. Security refresh: prevent malicious wear-out and increase durability for phase-change memory with dynamically randomized address mapping , 2010, ISCA.
[10] Hsien-Hsin S. Lee,et al. Smart Refresh: An Enhanced Memory Controller Design for Reducing Energy in Conventional and 3D Die-Stacked DRAMs , 2007, 40th Annual IEEE/ACM International Symposium on Microarchitecture (MICRO 2007).
[11] Tajana Simunic,et al. PDRAM: A hybrid PRAM and DRAM main memory system , 2009, 2009 46th ACM/IEEE Design Automation Conference.
[12] Hyunjin Lee,et al. Flip-N-Write: A simple deterministic technique to improve PRAM write performance, energy and endurance , 2009, 2009 42nd Annual IEEE/ACM International Symposium on Microarchitecture (MICRO).
[13] Byung-Gil Choi,et al. A 90 nm 1.8 V 512 Mb Diode-Switch PRAM With 266 MB/s Read Throughput , 2008, IEEE Journal of Solid-State Circuits.
[14] Duane Mills,et al. A 45nm 1Gb 1.8V phase-change memory , 2010, 2010 IEEE International Solid-State Circuits Conference - (ISSCC).
[15] Jun Yang,et al. A durable and energy efficient main memory using phase change memory technology , 2009, ISCA '09.
[16] Mircea R. Stan,et al. Bus-invert coding for low-power I/O , 1995, IEEE Trans. Very Large Scale Integr. Syst..
[17] Seung-Yun Lee,et al. A Low Power Phase-Change Random Access Memory using a Data-Comparison Write Scheme , 2007, 2007 IEEE International Symposium on Circuits and Systems.
[18] Vijayalakshmi Srinivasan,et al. Enhancing lifetime and security of PCM-based Main Memory with Start-Gap Wear Leveling , 2009, 2009 42nd Annual IEEE/ACM International Symposium on Microarchitecture (MICRO).
[19] Y.C. Chen,et al. Write Strategies for 2 and 4-bit Multi-Level Phase-Change Memory , 2007, 2007 IEEE International Electron Devices Meeting.
[20] Vijayalakshmi Srinivasan,et al. Scalable high performance main memory system using phase-change memory technology , 2009, ISCA '09.