Space Oblivious Compression: Power Reduction for Non-Volatile Main Memories

Power consumption of main memory has become a critical concern and has led to proposals to employ emerging non-volatile memories (NVMs) to replace or augment DRAM. This paper proposes Space Oblivious COmpression (SOCO), an in-place lightweight compression mechanism particularly designed for reducing NVM-based main-memory energy rather than saving space. SOCO can significantly reduce the number of bits written to save considerable energy for NVM-based main memories. By relaxing the goal of a conventional compression, the proposed approach practically eliminates memory addressing and management overheads incurred by compression techniques designed to save space. Our experiments show that SOCO provides more than 50% reduction in bits written, resulting in 23% and 34% energy savings for Spin-transfer Torque (STT)-MRAM and Phase Change Memory (PCM), respectively.

[1]  A. Robert Calderbank,et al.  Coset coding to extend the lifetime of memory , 2013, 2013 IEEE 19th International Symposium on High Performance Computer Architecture (HPCA).

[2]  Qingyuan Deng,et al.  MemScale: active low-power modes for main memory , 2011, ASPLOS XVI.

[3]  Yingwei Luo,et al.  Selective hardware/software memory virtualization , 2011, VEE '11.

[4]  Hyunjin Lee,et al.  Flip-N-Write: A simple deterministic technique to improve PRAM write performance, energy and endurance , 2009, 2009 42nd Annual IEEE/ACM International Symposium on Microarchitecture (MICRO).

[5]  Mahmut T. Kandemir,et al.  Evaluating STT-RAM as an energy-efficient main memory alternative , 2013, 2013 IEEE International Symposium on Performance Analysis of Systems and Software (ISPASS).

[6]  Vijay Janapa Reddi,et al.  PIN: a binary instrumentation tool for computer architecture research and education , 2004, WCAE '04.

[7]  Onur Mutlu,et al.  Base-delta-immediate compression: Practical data compression for on-chip caches , 2012, 2012 21st International Conference on Parallel Architectures and Compilation Techniques (PACT).

[8]  M. Ekman,et al.  A robust main-memory compression scheme , 2005, 32nd International Symposium on Computer Architecture (ISCA'05).

[9]  Kevin Skadron,et al.  A characterization of the Rodinia benchmark suite with comparison to contemporary CMP workloads , 2010, IEEE International Symposium on Workload Characterization (IISWC'10).

[10]  M. Hosomi,et al.  A novel nonvolatile memory with spin torque transfer magnetization switching: spin-ram , 2005, IEEE InternationalElectron Devices Meeting, 2005. IEDM Technical Digest..

[11]  Hubertus Franke,et al.  Memory Expansion Technology (MXT): Software support and performance , 2001, IBM J. Res. Dev..

[12]  Onur Mutlu,et al.  Architecting phase change memory as a scalable dram alternative , 2009, ISCA '09.

[13]  Kai Li,et al.  The PARSEC benchmark suite: Characterization and architectural implications , 2008, 2008 International Conference on Parallel Architectures and Compilation Techniques (PACT).

[14]  Rami G. Melhem,et al.  Delta-compressed caching for overcoming the write bandwidth limitation of hybrid main memory , 2013, TACO.

[15]  Rajeev Balasubramonian,et al.  MemZip: Exploring unconventional benefits from memory compression , 2014, 2014 IEEE 20th International Symposium on High Performance Computer Architecture (HPCA).

[16]  Onur Mutlu,et al.  Linearly compressed pages: A low-complexity, low-latency main memory compression framework , 2013, 2013 46th Annual IEEE/ACM International Symposium on Microarchitecture (MICRO).

[17]  Moinuddin K. Qureshi,et al.  Improving read performance of Phase Change Memories via Write Cancellation and Write Pausing , 2010, HPCA - 16 2010 The Sixteenth International Symposium on High-Performance Computer Architecture.

[18]  Amit Grover.  Analysis and Comparison: Full Adder Block in Submicron Technology , 2013, 2013 Fifth International Conference on Computational Intelligence, Modelling and Simulation.