Latch Offset Cancellation Sense Amplifier for Deep Submicrometer STT-RAM

As technology node shrinks, spin-transfer-torque random access memory (STT-RAM) has become a promising memory solution owing to its great scalability. However, the increase in process variation and decrease in the supply voltage result in the degradation of the read yield; thus, achieving the target read yield is an important issue in a deep-submicrometer technology node. In this paper, we propose a latch offset cancellation sense amplifier (LOC-SA) that cancels the latch offset with a compact area by merging the sensing circuit, latch sense amplifier, and write driver. By virtue of the latch offset cancellation characteristic, the voltage developing time can be significantly saved, leading to sensing-speed improvement. The Monte Carlo HSPICE simulation results using industry-compatible 45-nm model parameters show that the LOC-SA satisfies a target read yield of six-sigma (96.74% for 32 Mb) with more than 2 × faster sensing speed, 1.12 × lower read energy, and 1.13 × smaller area when compared with the best value of design parameters of other sense amplifiers.

[1]  Hui Zhao,et al.  A Scaling Roadmap and Performance Evaluation of In-Plane and Perpendicular MTJ Based STT-MRAMs for High-Density Cache Memory , 2013, IEEE Journal of Solid-State Circuits.

[2]  P. Stolk,et al.  Modeling statistical dopant fluctuations in MOS transistors , 1998 .

[3]  Seung H. Kang,et al.  A 45nm 1Mb embedded STT-MRAM with design techniques to minimize read-disturbance , 2011, 2011 Symposium on VLSI Circuits - Digest of Technical Papers.

[4]  Yoshihiro Ueda,et al.  A 64Mb MRAM with clamped-reference and adequate-reference schemes , 2010, 2010 IEEE International Solid-State Circuits Conference - (ISSCC).

[5]  Hanwool Jeong,et al.  Comparative Study of Various Latch-Type Sense Amplifiers , 2014, IEEE Transactions on Very Large Scale Integration (VLSI) Systems.

[6]  Meng-Fan Chang,et al.  An Offset-Tolerant Fast-Random-Read Current-Sampling-Based Sense Amplifier for Small-Cell-Current Nonvolatile Memory , 2013, IEEE Journal of Solid-State Circuits.

[7]  Kaushik Roy,et al.  Estimation of delay variations due to random-dopant fluctuations in nanoscale CMOS circuits , 2005 .

[8]  Ken Takeuchi.  Scaling challenges of NAND flash memory and hybrid memory system with storage class memory & NAND flash memory , 2013, Proceedings of the IEEE 2013 Custom Integrated Circuits Conference.

[9]  J. Meindl,et al.  The impact of intrinsic device fluctuations on CMOS SRAM cell stability , 2001, IEEE J. Solid State Circuits.

[10]  S. Watts,et al.  Latest Advances and Roadmap for In-Plane and Perpendicular STT-RAM , 2011, 2011 3rd IEEE International Memory Workshop (IMW).

[11]  Seong-Ook Jung,et al.  Reference-Scheme Study and Novel Reference Scheme for Deep Submicrometer STT-RAM , 2014, IEEE Transactions on Circuits and Systems I: Regular Papers.

[12]  Meng-Fan Chang,et al.  A High-Speed 7.2-ns Read-Write Random Access 4-Mb Embedded Resistive RAM (ReRAM) Macro Using Process-Variation-Tolerant Current-Mode Read Schemes , 2013, IEEE Journal of Solid-State Circuits.

[13]  Yiran Chen,et al.  Design of Last-Level On-Chip Cache Using Spin-Torque Transfer RAM (STT RAM) , 2011, IEEE Transactions on Very Large Scale Integration (VLSI) Systems.

[14]  Seong-Ook Jung,et al.  A Split-Path Sensing Circuit for Spin Torque Transfer MRAM , 2014, IEEE Transactions on Circuits and Systems II: Express Briefs.

[15]  Seong-Ook Jung,et al.  STT-MRAM Sensing Circuit With Self-Body Biasing in Deep Submicron Technologies , 2014, IEEE Transactions on Very Large Scale Integration (VLSI) Systems.

[16]  Yiran Chen,et al.  A 130 nm 1.2 V/3.3 V 16 Kb Spin-Transfer Torque Random Access Memory With Nondestructive Self-Reference Sensing Scheme , 2012, IEEE Journal of Solid-State Circuits.

[17]  Mark A. Taylor,et al.  A 45nm Self-Aligned-Contact Process 1Gb NOR Flash with 5MB/s Program Speed , 2008, 2008 IEEE International Solid-State Circuits Conference - Digest of Technical Papers.

[18]  Doris Schmitt-Landsiedel,et al.  Time-differential sense amplifier for sub-80mV bitline voltage embedded STT-MRAM in 40nm CMOS , 2013, 2013 IEEE International Solid-State Circuits Conference Digest of Technical Papers.

[19]  S. Ikeda,et al.  2 Mb SPRAM (SPin-Transfer Torque RAM) With Bit-by-Bit Bi-Directional Current Write and Parallelizing-Direction Current Read , 2008, IEEE Journal of Solid-State Circuits.

[20]  Seong-Ook Jung,et al.  An Offset-Canceling Triple-Stage Sensing Circuit for Deep Submicrometer STT-RAM , 2014, IEEE Transactions on Very Large Scale Integration (VLSI) Systems.

[21]  Kaushik Roy,et al.  Estimation of delay variations due to random-dopant fluctuations in nanoscale CMOS circuits , 2005, IEEE Journal of Solid-State Circuits.

[22]  M. Hosomi,et al.  A novel nonvolatile memory with spin torque transfer magnetization switching: spin-ram , 2005, IEEE InternationalElectron Devices Meeting, 2005. IEDM Technical Digest..

[23]  Luan Tran,et al.  45nm low power CMOS logic compatible embedded STT MRAM utilizing a reverse-connection 1T/1MTJ cell , 2009, 2009 IEEE International Electron Devices Meeting (IEDM).

[24]  Yiran Chen,et al.  Design Margin Exploration of Spin-Transfer Torque RAM (STT-RAM) in Scaled Technologies , 2010, IEEE Transactions on Very Large Scale Integration (VLSI) Systems.

[25]  Seong-Ook Jung,et al.  A Novel Sensing Circuit for Deep Submicron Spin Transfer Torque MRAM (STT-MRAM) , 2012, IEEE Transactions on Very Large Scale Integration (VLSI) Systems.

[26]  Chih-Kong Ken Yang,et al.  Reference Calibration of Body-Voltage Sensing Circuit for High-Speed STT-RAMs , 2013, IEEE Transactions on Circuits and Systems I: Regular Papers.

[27]  Sreedhar Natarajan,et al.  Cycling endurance optimization scheme for 1Mb STT-MRAM in 40nm technology , 2013, 2013 IEEE International Solid-State Circuits Conference Digest of Technical Papers.

[28]  William Song,et al.  Negative-resistance read and write schemes for STT-MRAM in 0.13µm CMOS , 2010, 2010 IEEE International Solid-State Circuits Conference - (ISSCC).