Phase Change Memory: From Devices to Systems

As conventional memory technologies such as DRAM and Flash run into scaling challenges, architects and system designers are forced to look at alternative technologies for building future computer systems. This synthesis lecture begins by listing the requirements for a next generation memory technology and briefly surveying the landscape of novel non-volatile memories. Among these, Phase Change Memory (PCM) is emerging as a leading contender, and the authors discuss the material, device, and circuit advances underlying this exciting technology. The lecture then describes architectural solutions to enable PCM for main memories. Finally, the authors explore the impact of such byte-addressable non-volatile memories on future storage and system designs. Table of Contents: Next Generation Memory Technologies / Architecting PCM for Main Memories / Tolerating Slow Writes in PCM / Wear Leveling for Durability / Wear Leveling Under Adversarial Settings / Error Resilience in Phase Change Memories / Storage and System Design With Emerging Non-Volatile Memories

[1]  Congyin Shi,et al.  Forming-Less Unipolar TaOx-Based RRAM with Large CC-Independence Range for High Density Memory Applications , 2010 .

[2]  A. Pirovano,et al.  Numerical Implementation of Low Field Resistance Drift for Phase Change Memory Simulations , 2008, 2008 Joint Non-Volatile Semiconductor Memory Workshop and International Conference on Memory Technology and Design.

[3]  K. Gopalakrishnan,et al.  Phase change memory technology , 2010, 1001.1164.

[4]  M. Yamaguchi,et al.  Novel multi-bit SONOS type flash memory using a high-k charge trapping layer , 2003, 2003 Symposium on VLSI Technology. Digest of Technical Papers (IEEE Cat. No.03CH37407).

[5]  Norman P. Jouppi,et al.  FREE-p: Protecting non-volatile memory against both hard and soft errors , 2011, 2011 IEEE 17th International Symposium on High Performance Computer Architecture.

[6]  Sejun Park,et al.  A highly manufacturable integration technology for 27nm 2 and 3bit/cell NAND flash memory , 2010, 2010 International Electron Devices Meeting.

[7]  Hsien-Hsin S. Lee,et al.  SAFER: Stuck-At-Fault Error Recovery for Memories , 2010, 2010 43rd Annual IEEE/ACM International Symposium on Microarchitecture.

[8]  Börje Johansson,et al.  Formation of large voids in the amorphous phase-change memory Ge2Sb2Te5 alloy. , 2009, Physical review letters.

[9]  Y. Liu,et al.  Highly uniform resistive switching characteristics of TiN/ZrO2/Pt memory devices , 2009 .

[10]  G. A. Fedde Design of a 1.5‐Million‐Bit Plated‐Wire Memory , 1966 .

[11]  Kailash Gopalakrishnan,et al.  Overview of candidate device technologies for storage-class memory , 2008, IBM J. Res. Dev..

[12]  Roy H. Campbell,et al.  Consistent and Durable Data Structures for Non-Volatile Byte-Addressable Memory , 2011, FAST.

[13]  M. Kozicki,et al.  Nanoscale memory elements based on solid-state electrolytes , 2005, IEEE Transactions on Nanotechnology.

[14]  William J. Gallagher,et al.  Development of the magnetic tunnel junction MRAM at IBM: From first junctions to a 16-Mb MRAM demonstrator chip , 2006, IBM J. Res. Dev..

[15]  M. Breitwisch,et al.  Novel Lithography-Independent Pore Phase Change Memory , 2007, 2007 IEEE Symposium on VLSI Technology.

[16]  R. Zonca,et al.  Crystal nucleation and growth processes in Ge2Sb2Te5 , 2004 .

[17]  Hamid Pirahesh,et al.  ARIES: a transaction recovery method supporting fine-granularity locking and partial rollbacks using write-ahead logging , 1998 .

[18]  Sivan Toledo,et al.  Algorithms and data structures for flash memories , 2005, CSUR.

[19]  G.E. Moore,et al.  Cramming More Components Onto Integrated Circuits , 1998, Proceedings of the IEEE.

[20]  Andrew Henry Bobeck New Concept in Large‐Size Memory Arrays—the Twistor , 1958 .

[21]  S. Ovshinsky Reversible Electrical Switching Phenomena in Disordered Structures , 1968 .

[22]  J. A. Aseltine,et al.  The application of amorphous materials to computer memories , 1973 .

[23]  B. Rajendran,et al.  Dynamic Resistance—A Metric for Variability Characterization of Phase-Change Memory , 2009, IEEE Electron Device Letters.

[24]  Roberto Bez,et al.  Introduction to flash memory , 2003, Proc. IEEE.

[25]  Daniel Christopher Worledge Single-domain model for toggle MRAM , 2006, IBM J. Res. Dev..

[26]  Mircea R. Stan,et al.  Relaxing non-volatility for fast and energy-efficient STT-RAM caches , 2011, 2011 IEEE 17th International Symposium on High Performance Computer Architecture.

[27]  H. Hwang,et al.  Uniform resistive switching with a thin reactive metal interface layer in metal-La0.7Ca0.3MnO3-metal heterostructures , 2008 .

[28]  G. Burr,et al.  Highly-scalable novel access device based on Mixed Ionic Electronic conduction (MIEC) materials for high density phase change memory (PCM) arrays , 2010, 2010 Symposium on VLSI Technology.

[29]  Rina Panigrahy,et al.  Design Tradeoffs for SSD Performance , 2008, USENIX ATC.

[30]  Hyung Gyu Lee,et al.  A PRAM and NAND flash hybrid architecture for high-performance embedded storage subsystems , 2008, EMSOFT '08.

[31]  Margo I. Seltzer,et al.  LIBTP: Portable, Modular Transactions for UNIX , 1992 .

[32]  M. Breitwisch,et al.  Ultra-Thin Phase-Change Bridge Memory Device Using GeSb , 2006, 2006 International Electron Devices Meeting.

[33]  H. Ohno,et al.  A multi-level-cell spin-transfer torque memory with series-stacked magnetotunnel junctions , 2010, 2010 Symposium on VLSI Technology.

[34]  Sivan Toledo,et al.  Competitive analysis of flash memory algorithms , 2011, TALG.

[35]  Bomy Chen,et al.  Multilevel Data Storage Characteristics of Phase Change Memory Cell with Doublelayer Chalcogenide Films (Ge2Sb2Te5 and Sb2Te3) , 2007 .

[36]  H.-S. Philip Wong,et al.  Phase Change Memory , 2010, Proceedings of the IEEE.

[37]  Makoto Kitagawa,et al.  A 4Mb conductive-bridge resistive memory with 2.3GB/s read-throughput and 216MB/s program-throughput , 2011, 2011 IEEE International Solid-State Circuits Conference.

[38]  D. Ielmini,et al.  Physical interpretation, modeling and impact on phase change memory (PCM) reliability of resistance drift due to chalcogenide structural relaxation , 2007, 2007 IEEE International Electron Devices Meeting.

[39]  Mann-Ho Cho,et al.  Structural Stability and Phase-Change Characteristics of Ge2Sb2Te5 ∕ SiO2 Nano-Multilayered Films , 2009 .

[40]  Y.J. Song,et al.  Two-bit cell operation in diode-switch phase change memory cells with 90nm technology , 2008, 2008 Symposium on VLSI Technology.

[41]  Dolores C. Miller,et al.  Direct observation of amorphous to crystalline phase transitions in nanoparticle arrays of phase change materials , 2007 .

[42]  F. Pellizzer,et al.  Characterization and modelling of low-frequency noise in PCM devices , 2008, 2008 IEEE International Electron Devices Meeting.

[43]  X. Y. Liu,et al.  Identification and application of current compliance failure phenomenon in RRAM device , 2010, Proceedings of 2010 International Symposium on VLSI Technology, System and Application.

[44]  Sudhanva Gurumurthi,et al.  Accelerating enterprise solid-state disks with non-volatile merge caching , 2010, International Conference on Green Computing.

[45]  Y. Iwata,et al.  Pipe-shaped BiCS flash memory with 16 stacked layers and multi-level-cell operation for ultra high density storage devices , 2006, 2009 Symposium on VLSI Technology.

[46]  Trevor N. Mudge,et al.  Improving NAND Flash Based Disk Caches , 2008, 2008 International Symposium on Computer Architecture.

[47]  Wei Xu,et al.  Using time-aware memory sensing to address resistance drift issue in multi-level phase change memory , 2010, 2010 11th International Symposium on Quality Electronic Design (ISQED).

[48]  R. Delhougne,et al.  Degradation of the Reset Switching During Endurance Testing of a Phase-Change Line Cell , 2009, IEEE Transactions on Electron Devices.

[49]  Alfred Menezes,et al.  Handbook of Applied Cryptography , 2018 .

[50]  Kinder,et al.  Large magnetoresistance at room temperature in ferromagnetic thin film tunnel junctions. , 1995, Physical review letters.

[51]  C. Davis,et al.  A 1024-bit nonvolatile 15ns bipolar read-write memory , 1978, 1978 IEEE International Solid-State Circuits Conference. Digest of Technical Papers.

[52]  Berger Emission of spin waves by a magnetic multilayer traversed by a current. , 1996, Physical review. B, Condensed matter.

[53]  A. Sawa,et al.  Colossal Electro-Resistance Memory Effect at Metal/La2CuO4 Interfaces , 2005 .

[54]  G. Servalli,et al.  A 45nm generation Phase Change Memory technology , 2009, 2009 IEEE International Electron Devices Meeting (IEDM).

[55]  C. Sie,et al.  Chalcogenide glass bistable resistivity (Ovonic) memories , 1970 .

[56]  K. Iida,et al.  An 8 MBYTE magnetic bubble memory , 1979 .

[57]  Kinam Kim,et al.  Technology for sub-50nm DRAM and NAND flash manufacturing , 2005, IEEE InternationalElectron Devices Meeting, 2005. IEDM Technical Digest..

[58]  C.T. Swift,et al.  A 6 V embedded 90 nm silicon nanocrystal nonvolatile memory , 2003, IEEE International Electron Devices Meeting 2003.

[59]  W. Haensch,et al.  Demonstration of highly scaled FinFET SRAM cells with high-κ/metal gate and investigation of characteristic variability for the 32 nm node and beyond , 2008, 2008 IEEE International Electron Devices Meeting.

[60]  Byung-Gil Choi,et al.  A 0.1-$\mu{\hbox {m}}$ 1.8-V 256-Mb Phase-Change Random Access Memory (PRAM) With 66-MHz Synchronous Burst-Read Operation , 2007, IEEE Journal of Solid-State Circuits.

[61]  John J. Shedletsky,et al.  Error Correction by Alternate-Data Retry , 1978, IEEE Transactions on Computers.

[62]  Rajesh K. Gupta,et al.  Moneta: A High-Performance Storage Array Architecture for Next-Generation, Non-volatile Memories , 2010, 2010 43rd Annual IEEE/ACM International Symposium on Microarchitecture.

[63]  Yi-Bo Liao,et al.  Operation of multi-level phase change memory using various programming techniques , 2009, 2009 IEEE International Conference on IC Design and Technology.

[64]  George M. Whitesides,et al.  Using self-assembly for the fabrication of nano-scale electronic and photonic devices , 2003 .

[65]  Tze-chiang Chen,et al.  Innovation in solid state devices for exascale computing , 2010, Proceedings of 2010 International Symposium on VLSI Technology, System and Application.

[66]  Y.C. Chen,et al.  Write Strategies for 2 and 4-bit Multi-Level Phase-Change Memory , 2007, 2007 IEEE International Electron Devices Meeting.

[67]  J. Rodgers,et al.  Chalcogenide memory arrays: characterization and radiation effects , 2003 .

[68]  K. Aratani,et al.  A Novel Resistance Memory with High Scalability and Nanosecond Switching , 2007, 2007 IEEE International Electron Devices Meeting.

[69]  B. Rajendran,et al.  Mechanisms of retention loss in Ge2Sb2Te5-based Phase-Change Memory , 2008, 2008 IEEE International Electron Devices Meeting.

[70]  Kinam Kim,et al.  Future Outlook of NAND Flash Technology for 40nm Node and Beyond , 2006, 2006 21st IEEE Non-Volatile Semiconductor Memory Workshop.

[71]  D. L. Critchlow,et al.  Solid state memory development in IBM , 1981 .

[72]  Moinuddin K. Qureshi,et al.  Improving read performance of Phase Change Memories via Write Cancellation and Write Pausing , 2010, HPCA - 16 2010 The Sixteenth International Symposium on High-Performance Computer Architecture.

[73]  Joe Brewer,et al.  Nonvolatile memory technologies with emphasis on flash , 2007 .

[74]  Kinam Kim,et al.  Comparison of double patterning technologies in NAND flash memory with sub-30nm node , 2009, 2009 Proceedings of the European Solid State Device Research Conference.

[75]  Tengyu Ma,et al.  Why is nonvolatile ferroelectric memory field-effect transistor still elusive? , 2002, IEEE Electron Device Letters.

[76]  H. Ishiwara Recent progress in ferroelectirc memory technology , 2006, 2006 8th International Conference on Solid-State and Integrated Circuit Technology Proceedings.

[77]  Se-Ho Lee,et al.  Highly scalable non-volatile and ultra-low-power phase-change nanowire memory. , 2007, Nature nanotechnology.

[78]  Sir Nevill Mott,et al.  The mechanism of threshold switching in amorphous alloys , 1978 .

[79]  P. Brown,et al.  A 0.18 /spl mu/m 4Mb toggling MRAM , 2003, IEEE International Electron Devices Meeting 2003.

[80]  D. Ielmini,et al.  Reliability issues and scaling projections for phase change non volatile memories , 2007, 2007 IEEE International Electron Devices Meeting.

[81]  G.W. Burr,et al.  Analytical model for RESET operation of Phase Change Memory , 2008, 2008 IEEE International Electron Devices Meeting.

[82]  D. R. Krahn,et al.  The design of a one megabit non-volatile M-R memory chip using 1.5*5 mu m cells , 1988 .

[83]  Shoichi Masui,et al.  A Passive UHF RFID Tag LSI with 36.6% Efficiency CMOS-Only Rectifier and Current-Mode Demodulator in 0.35/spl mu/m FeRAM Technology , 2006, 2006 IEEE International Solid State Circuits Conference - Digest of Technical Papers.

[84]  V. Speriosu,et al.  Spin-valve RAM cell , 1995 .

[85]  H. Hwang,et al.  TiO2-based metal-insulator-metal selection device for bipolar resistive random access memory cross-point application , 2011 .

[86]  A. Jagmohan,et al.  An area and latency assessment for coding for memories with stuck cells , 2010, 2010 IEEE Globecom Workshops.

[87]  M. Hosomi,et al.  A novel nonvolatile memory with spin torque transfer magnetization switching: spin-ram , 2005, IEEE InternationalElectron Devices Meeting, 2005. IEDM Technical Digest..

[88]  A. Sawa Resistive switching in transition metal oxides , 2008 .

[89]  J. Nowak,et al.  Switching distributions and write reliability of perpendicular spin torque MRAM , 2010, 2010 International Electron Devices Meeting.

[90]  M. Flynn,et al.  Parallel square and cube computations , 2000, Conference Record of the Thirty-Fourth Asilomar Conference on Signals, Systems and Computers (Cat. No.00CH37154).

[91]  Z. Wei,et al.  Highly reliable TaOx ReRAM and direct evidence of redox reaction mechanism , 2008, 2008 IEEE International Electron Devices Meeting.

[92]  Dongsoo Lee,et al.  Resistance switching of Al doped ZnO for Non Volatile Memory applications , 2006, 2006 21st IEEE Non-Volatile Semiconductor Memory Workshop.

[93]  Y. Inoue,et al.  High Speed Unipolar Switching Resistance RAM (RRAM) Technology , 2006, 2006 International Electron Devices Meeting.

[94]  H. Wong,et al.  Analysis of Temperature in Phase Change Memory Scaling , 2007, IEEE Electron Device Letters.

[95]  H.J. Kim,et al.  Programming disturbance and cell scaling in phase change memory: For up to 16nm based 4F2 cell , 2010, 2010 Symposium on VLSI Technology.

[96]  Frederick T. Chen,et al.  Low power and high speed bipolar switching with a thin reactive Ti buffer layer in robust HfO2 based RRAM , 2008, 2008 IEEE International Electron Devices Meeting.

[97]  Tomonori Sekiguchi,et al.  1-Tbyte/s 1-Gbit DRAM Architecture Using 3-D Interconnect for High-Throughput Computing , 2011, IEEE Journal of Solid-State Circuits.

[98]  M. Nagata,et al.  A novel stack capacitor cell for high density FeRAM compatible with CMOS logic , 2002, Digest. International Electron Devices Meeting,.

[99]  Charles Archer,et al.  Breaking the petaflops barrier , 2009, IBM J. Res. Dev..

[100]  V. Weidenhof,et al.  Structural transformations of Ge2Sb2Te5 films studied by electrical resistance measurements , 2000 .

[101]  André Seznec A Phase Change Memory as a Secure Main Memory , 2010, IEEE Computer Architecture Letters.

[102]  Yoshihiro Ueda,et al.  A 64Mb MRAM with clamped-reference and adequate-reference schemes , 2010, 2010 IEEE International Solid-State Circuits Conference - (ISSCC).

[103]  Bo Liu,et al.  Switching reliability improvement of phase change memory with nanoscale damascene structure by Ge2Sb2Te5 CMP process , 2008 .

[104]  Michael M. Swift,et al.  Mnemosyne: lightweight persistent memory , 2011, ASPLOS XVI.

[105]  John D. Davis,et al.  Block Management in Solid-State Devices , 2009, USENIX Annual Technical Conference.

[106]  Guido Torelli,et al.  A Bipolar-Selected Phase Change Memory Featuring Multi-Level Cell Storage , 2009, IEEE Journal of Solid-State Circuits.

[107]  Jongmoo Choi,et al.  Exploiting non-volatile RAM to enhance flash file system performance , 2007, EMSOFT '07.

[108]  X. Y. Liu,et al.  Current Compliance-Free Resistive Switching in Nonstoichiometric CeOx Films for Nonvolatile Memory Application , 2009, 2009 IEEE International Memory Workshop.

[109]  A. Panchula,et al.  Giant tunnelling magnetoresistance at room temperature with MgO (100) tunnel barriers , 2004, Nature materials.

[110]  S. Lai,et al.  OUM - A 180 nm nonvolatile memory cell element technology for stand alone and embedded applications , 2001, International Electron Devices Meeting. Technical Digest (Cat. No.01CH37224).

[111]  S. O. Park,et al.  Electrical observations of filamentary conductions for the resistive memory switching in NiO films , 2006 .

[112]  H. Hoenigschmid,et al.  A high-speed 128 Kbit MRAM core for future universal memory applications , 2003, 2003 Symposium on VLSI Circuits. Digest of Technical Papers (IEEE Cat. No.03CH37408).

[113]  Bruce Jacob,et al.  The performance of PC solid-state disks (SSDs) as a function of bandwidth, concurrency, device architecture, and system organization , 2009, ISCA '09.

[114]  G. Atwood,et al.  90nm Phase Change Technology with μTrench and Lance Cell Elements , 2007, 2007 International Symposium on VLSI Technology, Systems and Applications (VLSI-TSA).

[115]  J. Kim,et al.  Full Integration of Highly Manufacturable 512Mb PRAM based on 90nm Technology , 2006, 2006 International Electron Devices Meeting.

[116]  Yujong Kim,et al.  Colossal electroresistance mechanism in a Au ∕ Pr 0.7 Ca 0.3 Mn O 3 ∕ Pt sandwich structure: Evidence for a Mott transition , 2006 .

[117]  B. Kurdi,et al.  The micro to nano addressing block (MNAB) , 2005, IEEE InternationalElectron Devices Meeting, 2005. IEDM Technical Digest..

[118]  Y.N. Hwang,et al.  MLC PRAM with SLC write-speed and robust read scheme , 2010, 2010 Symposium on VLSI Technology.

[119]  Michael Luby,et al.  How to Construct Pseudo-Random Permutations from Pseudo-Random Functions (Abstract) , 1986, CRYPTO.

[120]  M. Aoki,et al.  Fully functional 0.5-/spl mu/m 64-kbit embedded SBT FeRAM using a new low temperature SBT deposition technique , 1999, 1999 Symposium on VLSI Technology. Digest of Technical Papers (IEEE Cat. No.99CH36325).

[121]  A. Pirovano,et al.  Threshold switching and phase transition numerical models for phase change memory simulations , 2008 .

[122]  C. Hagleitner,et al.  Device, circuit and system-level analysis of noise in multi-bit phase-change memory , 2010, 2010 International Electron Devices Meeting.

[123]  Lidong Zhou,et al.  Transactional Flash , 2008, OSDI.

[124]  Ute Drechsler,et al.  Transition-metal-oxide-based resistance-change memories , 2008, IBM J. Res. Dev..

[125]  Tseung-Yuen Tseng,et al.  Multilevel resistive switching in Ti/CuxO/Pt memory devices , 2010 .

[126]  Luis A. Lastras,et al.  Practical and secure PCM systems by online detection of malicious write streams , 2011, 2011 IEEE 17th International Symposium on High Performance Computer Architecture.

[127]  Simone Raoux,et al.  Crystallization properties of ultrathin phase change films , 2008 .

[128]  J. Slonczewski Current-driven excitation of magnetic multilayers , 1996 .

[129]  Stefan K. Lai,et al.  Flash memories: Successes and challenges , 2008, IBM J. Res. Dev..

[130]  A. Pirovano,et al.  Statistical analysis and modeling of programming and retention in PCM arrays , 2007, 2007 IEEE International Electron Devices Meeting.

[131]  B. Gleixner,et al.  Evolution of phase change memory characteristics with operating cycles: Electrical characterization and physical modeling , 2007 .

[132]  Susumu Kohyama,et al.  A Thermionic Electron Emission Model for Charge Retention in SAMOS Structure , 1982 .

[133]  L. V. Pieterson,et al.  Te-free, Sb-based phase-change materials for high-speed rewritable optical recording , 2003 .

[134]  Heng-Yuan Lee,et al.  A 4Mb embedded SLC resistive-RAM macro with 7.2ns read-write random-access time and 160ns MLC-access capability , 2011, 2011 IEEE International Solid-State Circuits Conference.

[135]  James R. Larus,et al.  Transactional Memory , 2006, Transactional Memory.

[136]  Y. Kato,et al.  0.18-/spl mu/m nondestructive readout FeRAM using charge compensation technique , 2005, IEEE Transactions on Electron Devices.

[137]  S. R. Ovshinsky,et al.  Reversible structural transformations in amorphous semiconductors for memory and logic , 1971 .

[138]  Chang Hua Siau,et al.  A 0.13µm 64Mb multi-layered conductive metal-oxide memory , 2010, 2010 IEEE International Solid-State Circuits Conference - (ISSCC).

[139]  Piero Olivo,et al.  Flash memory cells-an overview , 1997, Proc. IEEE.

[140]  Christopher Frost,et al.  Better I/O through byte-addressable, persistent memory , 2009, SOSP '09.

[141]  Eric A. Brewer,et al.  Stasis: flexible transactional storage , 2006, OSDI '06.

[142]  M. Breitwisch,et al.  On the dynamic resistance and reliability of phase change memory , 2008, 2008 Symposium on VLSI Technology.

[143]  Matthias Wuttig,et al.  Threshold field of phase change memory materials measured using phase change bridge devices , 2009 .

[144]  W. E. Beadle,et al.  Switching properties of thin Nio films , 1964 .

[145]  Daniele Ielmini,et al.  Threshold-Switching Delay Controlled by $\hbox{1}/f$ Current Fluctuations in Phase-Change Memory Devices , 2010, IEEE Transactions on Electron Devices.

[146]  Etienne,et al.  Giant magnetoresistance of (001)Fe/(001)Cr magnetic superlattices. , 1988, Physical review letters.

[147]  A. Pohm,et al.  Curie point written magnetoresistive memory , 2000 .

[148]  X.Q. Wei,et al.  HSPICE macromodel of PCRAM for binary and multilevel storage , 2006, IEEE Transactions on Electron Devices.

[149]  M. Durlam,et al.  Toggle MRAM: A highly-reliable Non-Volatile Memory , 2007, 2007 International Symposium on VLSI Technology, Systems and Applications (VLSI-TSA).

[150]  Daisaburo Takashima,et al.  High-density chain ferroelectric random access memory (chain FRAM) , 1997 .

[151]  Peter Desnoyers,et al.  Write Endurance in Flash Drives: Measurements and Analysis , 2010, FAST.

[152]  A. Sawa,et al.  Hysteretic current–voltage characteristics and resistance switching at a rectifying Ti∕Pr0.7Ca0.3MnO3 interface , 2004, cond-mat/0409657.

[153]  Rajesh K. Gupta,et al.  Onyx: A Prototype Phase Change Memory Storage Array , 2011, HotStorage.

[154]  N. Righos,et al.  A stackable cross point Phase Change Memory , 2009, 2009 IEEE International Electron Devices Meeting (IEDM).

[155]  Charles F. Pulvari,et al.  An Electrostatically Induced Permanent Memory , 1951 .

[156]  D. Ielmini,et al.  Phase Change Materials , 2009 .

[157]  Vijayalakshmi Srinivasan,et al.  Scalable high performance main memory system using phase-change memory technology , 2009, ISCA '09.

[158]  S. Q. Liu,et al.  Electric-pulse-induced reversible resistance change effect in magnetoresistive films , 2000 .

[159]  K. Rabe,et al.  Physics of thin-film ferroelectric oxides , 2005, cond-mat/0503372.

[160]  M. Klamkin,et al.  Extensions of the birthday surprise , 1967 .

[161]  Yin Hu,et al.  A new buried-channel EEPROM device , 1992 .

[162]  D. Ielmini,et al.  Reliability study of phase-change nonvolatile memories , 2004, IEEE Transactions on Device and Materials Reliability.

[163]  Masatoshi Imada,et al.  Metal-insulator transitions , 1998 .

[164]  C. Gerber,et al.  Reproducible switching effect in thin oxide films for memory applications , 2000 .

[165]  Balaram Sinharoy,et al.  POWER7: IBM's next generation server processor , 2010, 2009 IEEE Hot Chips 21 Symposium (HCS).

[166]  B. Rajendran,et al.  Low Thermal Budget Processing for Sequential 3-D IC Fabrication , 2007, IEEE Transactions on Electron Devices.

[167]  C. Zambelli,et al.  Set of Electrical Characteristic Parameters Suitable for Reliability Analysis of Multimegabit Phase Change Memory Arrays , 2008, 2008 Joint Non-Volatile Semiconductor Memory Workshop and International Conference on Memory Technology and Design.

[168]  Yiran Chen,et al.  A novel architecture of the 3D stacked MRAM L2 cache for CMPs , 2009, 2009 IEEE 15th International Symposium on High Performance Computer Architecture.

[169]  U-In Chung,et al.  A unified 7.5nm dash-type confined cell for high performance PRAM device , 2008, 2008 IEEE International Electron Devices Meeting.

[170]  E. Pop,et al.  Multiphysics Modeling and Impact of Thermal Boundary Resistance in Phase Change Memory Devices , 2006, Thermal and Thermomechanical Proceedings 10th Intersociety Conference on Phenomena in Electronics Systems, 2006. ITHERM 2006..

[171]  Sung-Soo Lee,et al.  A 7MB/s 64Gb 3-bit/cell DDR NAND flash memory in 20nm-node technology , 2011, 2011 IEEE International Solid-State Circuits Conference.

[172]  Yeonwoong Jung,et al.  Extremely low drift of resistance and threshold voltage in amorphous phase change nanowire devices , 2010 .

[173]  Frederick T. Chen,et al.  Evidence and solution of over-RESET problem for HfOX based resistive memory with sub-ns switching speed and high endurance , 2010, 2010 International Electron Devices Meeting.

[174]  R. Womack,et al.  A non-volatile memory cell based on ferroelectric storage capacitors , 1987, 1987 International Electron Devices Meeting.

[175]  H. Ohno,et al.  Tunnel magnetoresistance of 604% at 300K by suppression of Ta diffusion in CoFeB∕MgO∕CoFeB pseudo-spin-valves annealed at high temperature , 2008 .

[176]  Hye-Jin Kim,et al.  A 90nm 1.8V 512Mb Diode-Switch PRAM with 266MB/s Read Throughput , 2007, 2007 IEEE International Solid-State Circuits Conference. Digest of Technical Papers.

[177]  Rajesh K. Gupta,et al.  NV-Heaps: making persistent objects fast and safe with next-generation, non-volatile memories , 2011, ASPLOS XVI.

[178]  S. Chou,et al.  Imprint Lithography with 25-Nanometer Resolution , 1996, Science.

[179]  Helen Grampeix,et al.  Resistance switching in HfO2 metal-insulator-metal devices , 2010 .

[180]  Lin Li,et al.  Driving Device Comparison for Phase-Change Memory , 2011, IEEE Transactions on Electron Devices.

[181]  A. Driskill-Smith,et al.  Fully integrated 54nm STT-RAM with the smallest bit cell dimension for high density memory application , 2010, 2010 International Electron Devices Meeting.