Navin K. Mishra

A Tri-Modal 20-Gbps/Link Differential/DDR3/GDDR5 Memory Interface

Ting Wu, Manish Jain, Amir Amirkhany, 2012, IEEE Journal of Solid-State Circuits.

A 12.8-Gb/s/link Tri-Modal Single-Ended Memory Interface

Ting Wu, Manish Jain, Amir Amirkhany, 2012, IEEE Journal of Solid-State Circuits.

An output structure for a bi-modal 6.4-Gbps GDDR5 and 2.4-Gbps DDR3 compatible memory interface

Manish Jain, Amir Amirkhany, Sanku Mukherjee, 2011, 2011 IEEE Custom Integrated Circuits Conference (CICC).

A 2.5Gbps Quad CMOS Transceiver Cell Using Regulated Supply Low Jitter PLL

Manish Jain, Kapil Vyas, Mahabaleshwara, 2007, 20th International Conference on VLSI Design held jointly with 6th International Conference on Embedded Systems (VLSID'07).