Fast Random Walk Based Capacitance Extraction for the 3-D IC Structures With Cylindrical Inter-Tier-Vias
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[1] Francisco Bernal,et al. A Stochastic Algorithm Based on Fast Marching for Automatic Capacitance Extraction in Non-Manhattan Geometries , 2014, SIAM J. Imaging Sci..
[2] Chi-Ok Hwang,et al. epsilon-Shell error analysis for "Walk On Spheres" algorithms , 2003, Math. Comput. Simul..
[3] Weiping Shi,et al. Fast 3-D Capacitance Extraction by Inexact Factorization and Reduction , 2006, IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems.
[4] Luca Daniel,et al. A hierarchical floating random walk algorithm for fabric-aware 3D capacitance extraction , 2009, 2009 IEEE/ACM International Conference on Computer-Aided Design - Digest of Technical Papers.
[5] Ieee Circuits,et al. IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems information for authors , 2018, IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems.
[6] Jacob K. White,et al. FastCap: a multipole accelerated 3-D capacitance extraction program , 1991, IEEE Trans. Comput. Aided Des. Integr. Circuits Syst..
[7] Sung Kyu Lim,et al. Fast and accurate full-chip extraction and optimization of TSV-to-wire coupling , 2014, 2014 51st ACM/EDAC/IEEE Design Automation Conference (DAC).
[8] E. Friedman,et al. Closed-Form Expressions of 3-D Via Resistance, Inductance, and Capacitance , 2009, IEEE Transactions on Electron Devices.
[9] Qing Wang,et al. Random walk based capacitance extraction for 3D ICs with cylindrical inter-tier-vias , 2014, 2014 IEEE/ACM International Conference on Computer-Aided Design (ICCAD).
[10] W. Dehaene,et al. Electrical Modeling and Characterization of Through Silicon via for Three-Dimensional ICs , 2010, IEEE Transactions on Electron Devices.
[11] R. B. Iverson,et al. A stochastic algorithm for high speed capacitance extraction in integrated circuits , 1992 .
[12] Hao Yu,et al. Reliable 3-D Clock-Tree Synthesis Considering Nonlinear Capacitive TSV Model With Electrical–Thermal–Mechanical Coupling , 2013, IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems.
[13] Wenjian Yu,et al. Efficient Space Management Techniques for Large-Scale Interconnect Capacitance Extraction With Floating Random Walks , 2013, IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems.
[14] Sung Kyu Lim,et al. High-density integration of functional modules using monolithic 3D-IC technology , 2013, 2013 18th Asia and South Pacific Design Automation Conference (ASP-DAC).
[15] Madhav P. Desai,et al. Variance reduction in Monte Carlo capacitance extraction , 2005, 18th International Conference on VLSI Design held jointly with 4th International Conference on Embedded Systems Design.
[16] Sung Kyu Lim,et al. Power benefit study for ultra-high density transistor-level monolithic 3D ICs , 2013, 2013 50th ACM/EDAC/IEEE Design Automation Conference (DAC).
[17] M. Mascagni,et al. The simulation-tabulation method for classical diffusion Monte Carlo , 2001 .
[18] Rajiv V. Joshi,et al. 3-D-TCAD-Based Parasitic Capacitance Extraction for Emerging Multigate Devices and Circuits , 2013, IEEE Transactions on Very Large Scale Integration (VLSI) Systems.
[19] Wenjian Yu,et al. Advanced Field-Solver Techniques for RC Extraction of Integrated Circuits , 2014 .
[20] Wenjian Yu,et al. Enhanced QMM-BEM solver for three-dimensional multiple-dielectric capacitance extraction within the finite domain , 2004, IEEE Transactions on Microwave Theory and Techniques.
[21] S. Mukhopadhyay,et al. Fast and Accurate Analytical Modeling of Through-Silicon-Via Capacitive Coupling , 2011, IEEE Transactions on Components, Packaging and Manufacturing Technology.
[22] Mattan Kamon,et al. High-Accuracy Parasitic Extraction , 2016 .
[23] Sung Kyu Lim,et al. On accurate full-chip extraction and optimization of TSV-to-TSV coupling elements in 3D ICs , 2013, 2013 IEEE/ACM International Conference on Computer-Aided Design (ICCAD).
[24] Sung Kyu Lim,et al. A design tradeoff study with monolithic 3D integration , 2012, Thirteenth International Symposium on Quality Electronic Design (ISQED).
[25] Chenyun Pan,et al. System-level analysis for 3D interconnection networks , 2013, 2013 IEEE International Interconnect Technology Conference - IITC.
[26] Weiping Shi,et al. A fast hierarchical algorithm for three-dimensional capacitanceextraction , 2002, IEEE Trans. Comput. Aided Des. Integr. Circuits Syst..
[27] Cheng-Kok Koh,et al. A direct integral-equation solver of linear complexity for large-scale 3D capacitance and impedance extraction , 2009, 2009 46th ACM/IEEE Design Automation Conference.
[28] Wenjian Yu,et al. Efficient techniques for the capacitance extraction of chip-scale VLSI interconnects using floating random walk algorithm , 2014, 2014 19th Asia and South Pacific Design Automation Conference (ASP-DAC).
[29] Zhi Liu,et al. RWCap: A Floating Random Walk Solver for 3-D Capacitance Extraction of Very-Large-Scale Integration Interconnects , 2013, IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems.